In a traditional front-mounted chip package assembly, the inactive face of a chip may be attached to a chip carrier substrate of a lead frame, while electrodes on the active face of the chip are connected to leads that lie around the carrier substrate via metal wires. This can couple the electrodes on the active face of the chip to an external circuit. However, such an approach may not be best suited to meet various semiconductor package size and thickness requirements with increasing demands on miniaturization, light weight, and multi-functionality of electronic components. In such a traditional package assembly utilizing wire bonding, because of the distance between leads and the carrier substrate, and the lead size, the height of the package assembly may be relatively large. In addition, there may be a relatively large parasitic resistance in the package assembly when metal wires are appthat lies to lead out electrodes, which can adversely affect the package quality.